Market Share
~20% custom cloud AI ASIC (growing); #2 data center networking PHY
Key Product
OCTEON network processors, custom cloud AI ASICs, 400G/800G Ethernet PHYs
Full briefing▼ Expand
Marvell Technology, Inc. (NASDAQ: MRVL) is headquartered in Santa Clara, California, and designs semiconductor solutions for data infrastructure, 5G carrier infrastructure, enterprise networking, and automotive applications. Founded in 1997 by Sehat Sutardja and Weili Dai, Marvell has grown through numerous acquisitions — including Cavium (2018, $6B, for network processors and security ASICs) and Inphi (2021, $10B, for high-speed optical interconnects). In the AI data center supply chain, Marvell occupies a critical but under-recognized position as the designer of custom silicon for hyperscaler networking. Its key products include: (1) OCTEON 10 network processors — Arm-based SoCs used in SmartNICs, data processing units (DPUs), and network switches within AI server racks; (2) 400G/800G DSP-based Ethernet PHYs — the chips that drive high-speed optical transceivers connecting AI GPU nodes; and (3) Custom cloud ASICs — purpose-built chips co-designed with individual hyperscalers for workload-specific acceleration. Marvell's custom ASIC business is its fastest-growing segment. It has disclosed design wins with multiple hyperscalers for AI infrastructure silicon — chips that handle data movement, compression, security processing, and storage acceleration in ways that would otherwise consume expensive GPU compute cycles. This positions Marvell alongside Broadcom as the second key ASIC partner for hyperscalers building custom silicon stacks. All advanced Marvell chips are fabricated by TSMC on N5 (5nm) and N4P nodes. Mature-node networking and storage controllers come from GlobalFoundries and UMC at 28nm–40nm. Marvell licenses Arm IP for its OCTEON Arm cores and collaborates with TSMC on advanced packaging (CoWoS) for high-bandwidth memory integration in some products. Marvell has significant China exposure (~10–15% of revenue) through its storage controller and 5G baseband chip business, making it subject to export control risk as the US tightens restrictions on semiconductor technology transfers to Chinese entities.
Critical path — raw silicon to deployment
FOUNDRIES
TSMC ▲
CoWoS advanced packaging, N3/N2 logic
EDA TOOLS
Cadence ▲
Virtuoso (analog), Genus/Innovus (digital synthesis), Tempus (timing signoff)
EDA TOOLS
Synopsys ▲
Design Compiler (synthesis), PrimeTime (timing), VCS (simulation), IC Compiler 2
CHIP DESIGNERS
Marvell
OCTEON network processors, custom cloud AI ASICs, 400G/800G Ethernet PHYs
NETWORKING
Arista Networks
7050X4/7060X5 AI cluster switches, 7800 modular chassis, CloudVision
AI CONSUMERS
Meta
MTIA v2 AI accelerator, H100/H200 GPU clusters (Llama models)