ASE Technology

ASE Technology Holding Co., Ltd.

🇹🇼
OSAT / PACKAGING🇹🇼 TWASX · NYSE | 3711 · TWSE
aseglobal.com

Market Share

~30% global OSAT revenue

Key Product

Flip-chip BGA, wire-bond, SiP, fan-out packaging

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ASE Technology Holding Co., Ltd. (NYSE: ASX; TWSE: 3711) is headquartered in Kaohsiung, Taiwan, and controls approximately 30% of global OSAT revenue. Formed through the 2018 merger of Advanced Semiconductor Engineering and Siliconware Precision Industries (SPIL), ASE operates over 30 manufacturing facilities across Taiwan, China, South Korea, Malaysia, and Japan. In the AI chip supply chain, ASE performs the critical post-fabrication steps that transform raw silicon dies from TSMC or Samsung Foundry into packaged modules. For NVIDIA's H100 and H200 GPUs, this means mounting the CoWoS-packaged die onto a substrate, attaching it to a PCB carrier, running electrical tests, and shipping to Supermicro, Quanta Computer, or other ODMs for server assembly. The entire production ramp of NVIDIA's Blackwell B200 and GB200 systems depends on OSAT capacity at ASE and Amkor. ASE's key packaging technologies include flip-chip ball grid array (FC-BGA), which connects die to substrate using solder bumps rather than wire bonds for lower resistance and higher bandwidth; System-in-Package (SiP), which integrates multiple dies, passives, and RF components in a single module (widely used in Apple Watch and AirPods); and fan-out wafer-level packaging (FOWLP), which routes connections outside the die footprint without a substrate. Packaging and test account for approximately 10–15% of total chip manufacturing cost but are a disproportionate bottleneck during supply crunches. When NVIDIA's CoWoS capacity at TSMC was constrained in 2023–2024, downstream assembly at ASE and Amkor became the limiting factor for GPU shipments to hyperscalers. ASE has invested heavily in advanced heterogeneous integration — specifically in 2.5D and 3D packaging processes that stack chiplets on silicon interposers. These technologies are increasingly important as chip designers move to disaggregated chiplet architectures to work around reticle limits and improve yield.

Critical path — raw silicon to deployment

FOUNDRIES

TSMC

CoWoS advanced packaging, N3/N2 logic

FOUNDRIES

Samsung Foundry

GAA 3nm logic, advanced packaging

OSAT / PACKAGING

ASE Technology

Flip-chip BGA, wire-bond, SiP, fan-out packaging

CHIP DESIGNERS

NVIDIA

H100, H200, Blackwell B200 GPUs

EDGE DEVICES

Apple

M4, A18 Pro SoC (on-device AI, Neural Engine)