JCET Group

JCET Group Co., Ltd. (长电科技; SH: 600584) is headquartered in Jiangyin, Jiangsu Province, and traces its roots to a state-owned semiconductor assembly plant established in the city decades ago before restructuring into its modern corporate form. JCET expanded rapidly through acquisition, most significantly with its 2015 purchase of Singapore-based STATS ChipPAC — at the time one of the largest outbound acquisitions ever completed by a Chinese semiconductor company — which gave JCET advanced packaging technology, a global customer base, and manufacturing footprint outside China that its pure-domestic rivals lacked. That acquisition transformed JCET from a mid-tier domestic assembly house into a company capable of competing directly with the world's largest OSAT (outsourced semiconductor assembly and test) providers. OSAT sits toward the back end of the semiconductor supply chain: after a foundry like SMIC, TSMC, or Hua Hong fabricates a wafer, the individual chips must be cut, packaged into the plastic or ceramic housings that protect them and connect them electrically to circuit boards, and tested for defects before shipment — work that OSAT companies perform on an outsourced basis for chipmakers who don't operate their own back-end facilities. JCET is now the world's third-largest OSAT by revenue, behind Taiwan's ASE Technology (roughly $18.5 billion in revenue and about 44.6% share of the combined top-10 OSAT market) and the US's Amkor (roughly $6.3 billion, about 15% share). JCET's own revenue reached approximately $5.0 billion in its most recent full fiscal year, up 19.3% year-over-year, giving it roughly 12% of the top-10 OSAT market and firmly cementing its position as the largest OSAT company headquartered in China — a tier of the supply chain that ranks below foundries and chip designers in visibility but remains structurally essential, since no chip reaches a customer without back-end packaging and test regardless of how advanced its fabrication. The most consequential recent development for JCET is its accelerating push into advanced packaging — specifically 2.5D and 3D integration technologies that stack or tightly interconnect multiple chiplets and high-bandwidth memory (HBM) dies using silicon interposers or through-silicon vias, roughly analogous to the CoWoS-style packaging TSMC uses for NVIDIA's AI accelerators. Advanced packaging has become the single most strategically important segment of the OSAT industry because of the AI buildout: as chipmakers increasingly assemble AI processors from multiple smaller chiplets rather than one large monolithic die, and pair those chiplets with stacks of HBM for memory bandwidth, the packaging step that binds them together has become as technically demanding — and as commercially valuable — as front-end fabrication itself. Advanced packaging commands ASPs (average selling prices) roughly 3-10x higher than traditional wire-bond packaging, the same dynamic that has pushed ASE and Amkor to expand their own advanced-packaging capacity aggressively in Taiwan, Korea, and the US. In 2026, JCET announced a RMB 7.8 billion (roughly $1.1-1.15 billion) investment to build a new advanced-packaging and testing plant in Shanghai's Lin-gang Special Area, structured through a controlled subsidiary and rolled out in two phases, with the first phase — covering factory construction and equipment installation — targeted for completion in the second half of 2028. The plant is explicitly aimed at HPC, HBM, and chiplet-integration demand, positioning JCET to capture a larger share of China's AI-driven packaging spending as Chinese AI chip designers scale output. JCET was not alone in this move: in the first half of 2026 alone, four Chinese A-share packaging companies — JCET, Tongfu Microelectronics, Huatian Technology, and Forehope Electronic — collectively announced more than RMB 27 billion in advanced-packaging expansion investment, underscoring how central this capacity race has become to China's broader AI hardware strategy. JCET's relationship to the rest of China's chip supply chain runs through its role as the outsourced back-end for SMIC and Hua Hong, packaging the wafers those foundries fabricate before they reach end customers, and it supplies packaged modules that feed into chip lines associated with Huawei/HiSilicon. Unlike the equipment, lithography, and EDA layers of China's semiconductor stack, OSAT has so far remained largely outside the direct scope of US export controls — packaging and test equipment is generally less exposed to Entity List restrictions than front-end fabrication tools, and JCET itself has not been the target of the kind of BIS or DoD designations that have constrained NAURA, AMEC, SMEE, or Chinese chip designers like Cambricon. That relative insulation, combined with the AI-driven pricing premium now attached to advanced packaging specifically, gives JCET a comparatively unconstrained growth runway even as much of the rest of China's chip industry navigates an increasingly restrictive external environment — though JCET's ultimate ceiling still depends on how much of the world's most advanced chip production, and therefore packaging demand, continues to flow toward TSMC and Samsung Foundry rather than SMIC and Hua Hong.